1. Field of the Invention
This invention generally relates to setting up a wafer inspection process using programmed defects.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as ICs. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail.
There are a number of currently used methods for setting up inspection process recipes. For example, one current method includes taking a wafer (covered in chips) with an unknown number and location of patterned defects (potentially none) and inspecting the wafer with “historically commonly used modes” and a substantially low threshold. The substantially low threshold means that a substantial amount of noise will likely be detected together with defects of interest and all of the detected events need to be reviewed arduously on a scanning electron microscope (SEM) until at least a few pattern defects are found and separated from the noise. Then, the pattern defect locations can be driven to on the inspector to check all or most of the modes to see which has the highest signal for the defects already found.
One disadvantage of this method is that choosing the optimum mode is often unintuitive. For example, the shortest available wavelength on a wafer inspection system doesn't always provide the best signal for a given defect type. In addition, most of the production wafers used for bright field (BF) recipe setup will not contain all types of pattern defects (“types” being a combination of size, shape, location, etc.) or even a very limited number of any one type of pattern defect of interest. As such, the best mode for each potential defect type cannot be known without using many, many wafers for mode data collection. Therefore, data collection takes a significant time or, more often, a fab chooses to take a chance on a limited signal/noise data set thereby running the risk of missing certain killer defect types, which would cause wafer yield crashes and lead to less sellable chips.
Another currently used method involves placing programmed defects inside test chips (as opposed to product/sellable chips), and the best mode is found using those programmed defects. Noise information is also gathered on the test chips. However, test chips cannot represent all types of production chips. In addition, the production chips can vary widely in background pattern. The background pattern under and next to a programmed defect will alter the mode that is best at catching it. Therefore, if there are differences in the background pattern of the test chip and the product or sellable chip, then it is possible that the mode selected as the best mode using the test chip may not actually be the best mode for detecting the defects in the product chip. Furthermore, often, test chips are run on a process that evolves over time. Therefore, if a best mode was selected using programmed defects on a test chip, it may no longer apply to current production chips.
An additional currently used method involves placing programmed defects in scribe areas on a wafer. The scribe areas may be next to test chips or product/sellable chips. The best mode may then be found using these programmed defects. Such methods also, however, have a number of disadvantages. For example, the noise data may not be collected at all or may be only collected on the scribe structure. Therefore, the noise data may be local noise and not representative of the true wafer-wide or chip-wide worst case scenario for noise. In addition, the background pattern and typically the film stacks and film uniformity are different in the scribe lane compared to that in-die on production chips. For example, the scribe lanes typically contain test pads and targets for measuring thickness, overlay, critical dimensions, etc. These differences can lead to selection of a mode that is the best for detection of defects in the scribe lane but that is not the best for detecting defects in the production chip, which is where inspection really matters. Furthermore, the scribe area will later be used to cut up the wafer (for dicing) thereby separating the chips, so control of the process in these areas is typically far poorer that in-die controls because the scribe area has no direct impact on chip functionality and yields. Therefore, picking the best mode(s) using programmed defects placed in the scribe area is likely to lead to the wrong mode being selected since there are significant differences between scribe and in-die areas.
Accordingly, it would be advantageous to develop methods and/or systems for wafer inspection setup that do not have one or more of the disadvantages described above.